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我的主机内存现在是:PC4200 DDR2, 三星的,详细资料如下。我想问:
我这个就是533的DDR2吗?为什么它说速度是266.7?
如果我想加内存,怎么加?主机上还有两条槽。
我的CPU是930,总线是800MHz.
Memory --------------------------------------------------------------------
Total Memory Size: 1024 MBytes
Total Memory Size [MB]: 1024
Current Memory Clock: 266.0 MHz
Current Timing (tCAS-tRCD-tRP-tRAS): 4.0-4-4-11
Memory Runs At: Dual-Channel Interleaved
Row: 0 - 512 MB PC4200 DDR2-SDRAM Samsung M3 78T6553CZ3-CD5 --------------
Module Number: 0
Module Size: 512 MBytes
Memory Type: DDR2-SDRAM
DIMM Type: Regular Unbuffered (UDIMM)
Error Check/Correction: None
Memory Speed: 266.7 MHz (PC4200)
Module Manufacturer: Samsung
Module Model: M3 78T6553CZ3-CD5
Serial Number: 1049301494
Manufacturing Date: Year: 2006, Week: 23
Module Width: 64-bits
Module Voltage: SSTL 1.8V
SPD Revision: 1.2
Number Of Ranks: 1
Row Address Bits: 14
Column Address Bits: 10
Number Of Banks: 4
Supported Burst Lengths: 4, 8
Refresh Rate: Reduced 0.5x (7.8 us)
Supported CAS Latency: 3.0 (5.00 ns @ 200.0 MHz), 4.0 (3.75 ns @ 266.7 MHz), 5.0 (3.75 ns @ 266.7 MHz)
Min. Row Precharge Time (tRP): 15.00 ns
Min. Row-Activate To Row-Activate Delay (tRRD): 7.50 ns
Min. RAS-to-CAS Delay (tRCD): 15.00 ns
Min. RAS Pulse Width (tRAS): 40 ns
Address and Command Setup Time Before Clock (tIS): 0.25 ns
Address and Command Setup Time After Clock (tIH): 0.37 ns
Data Input Setup Time Before Strobe (tDS): 0.10 ns
Data Input Setup Time After Strobe (tDH): 0.22 ns
Write Recovery Time (tWR): 15.00 ns
Internal write to read command delay (tWTR): 7.50 ns
Internal read to precharge command delay (tRTP): 7.50 ns
Row: 2 - 512 MB PC4200 DDR2-SDRAM Samsung M3 78T6553CZ3-CD5 --------------
Module Number: 2
Module Size: 512 MBytes
Memory Type: DDR2-SDRAM
DIMM Type: Regular Unbuffered (UDIMM)
Error Check/Correction: None
Memory Speed: 266.7 MHz (PC4200)
Module Manufacturer: Samsung
Module Model: M3 78T6553CZ3-CD5
Serial Number: 1066078710
Manufacturing Date: Year: 2006, Week: 23
Module Width: 64-bits
Module Voltage: SSTL 1.8V
SPD Revision: 1.2
Number Of Ranks: 1
Row Address Bits: 14
Column Address Bits: 10
Number Of Banks: 4
Supported Burst Lengths: 4, 8
Refresh Rate: Reduced 0.5x (7.8 us)
Supported CAS Latency: 3.0 (5.00 ns @ 200.0 MHz), 4.0 (3.75 ns @ 266.7 MHz), 5.0 (3.75 ns @ 266.7 MHz)
Min. Row Precharge Time (tRP): 15.00 ns
Min. Row-Activate To Row-Activate Delay (tRRD): 7.50 ns
Min. RAS-to-CAS Delay (tRCD): 15.00 ns
Min. RAS Pulse Width (tRAS): 40 ns
Address and Command Setup Time Before Clock (tIS): 0.25 ns
Address and Command Setup Time After Clock (tIH): 0.37 ns
Data Input Setup Time Before Strobe (tDS): 0.10 ns
Data Input Setup Time After Strobe (tDH): 0.22 ns
Write Recovery Time (tWR): 15.00 ns
Internal write to read command delay (tWTR): 7.50 ns
Internal read to precharge command delay (tRTP): 7.50 ns |
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